SystemC provides an industry standard means of modeling and verifying hardware and systems using standard software compilers. All the material required to simulate SystemC using a standard C++ compiler, such as Microsoft Visual C++ or GNU GCC, can be downloaded free of charge from the SystemC website (

SystemC is a worldwide standard, supported by a broad range of companies.
for (sc_int<3> i = 0; i < 7; i++) {
x[i] = a[i] * b[i];

SystemC consists of a set of class libraries for C++ that describe hardware constructs and concepts. This means that you can develop cycle-accurate models of hardware, software and interfaces, which can be simulated and debugged within your existing C++ development environment.

SystemC allows the initial design, debugging and refinement to be performed using the same test benches, which eliminates translation errors, and allows fast, easy verification.

Since SystemC uses standard C++, the productivity benefits offered to software engineers for years are now available to hardware and system designers. SystemC is more compact than VHDL or Verilog and, as a result, is faster to write and more maintainable and readable. It can be compiled into a fast, executable specification.


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