SystemC was originally developed as a system modelling and verification tool, and still required manual translation to a hardware description language to produce hardware.

SystemCrafter SC automates this process, by quickly synthesizing SystemC to RTL VHDL or Verilog. It will also generate a SystemC description of the synthesized circuit, which can be used to verify the synthesized code using your existing test harness.

SystemCrafter SC quickly synthesizes SystemC to RTL VHDL or Verilog, and generates synthesized SystemC for verification.
for (sc_int<3> i = 0; i < 7; i++) {
x[i] = a[i] * b[i];
wait();
}

SystemCrafter SC gives the designer control of the critical steps of scheduling (clock cycle allocation) and allocation (hardware reuse). Thus, the results are always predictable, controllable and match the designer's expectations.

SystemCrafter SC allows you to develop, refine, debug and synthesize hardware and systems within your existing C++ compiler's development environment. You can run fast, executable SystemC specifications to verify your design. You can configure your compiler so that SystemCrafter SC is automatically run when you specify that you want to generate hardware. There is no new GUI to learn.

SystemCrafter SC can be used for:


Synthesizing SystemC to Hardware



A typical development process is:

  • Use your existing C++ development environment to:

    • Develop an initial SystemC description.
    • Write a test bench.
    • Debug, simulate and verify your description.
    • Refine it to describe more efficient hardware.
    • Experiment with trade-offs.
    • Verify the refined description using your test bench.
    • SystemCrafter SC will synthesize your SystemC description to RTL VHDL or Verilog, and a SystemC description of the HDL.
    • Verify the synthesized SystemC model.
  • Use your existing VHDL or Verilog synthesis tool and hardware flow (such as Xilinx XST and Project Navigator) to:

    • Synthesize the generated HDL to working hardware.


System-level Design and Co-design



The additional advantage of SystemCrafter SC for co-design is that you can simulate the hardware and software partitions in the same framework. A typical development process is to:

  • Use your existing C++ development environment to:

    • Develop an initial SystemC description.
    • Write a test bench.
    • Debug, simulate and verify your description.
    • Partition the design into hardware, software and interfaces.
    • Verify the partitioned description using your test bench.
    • Refine it to describe more efficient hardware.
    • Experiment with trade-offs.
    • Verify the refined description using your test bench.
    • SystemCrafter SC will synthesize the hardware parts of your SystemC description to RTL VHDL or Verilog, and a SystemC description of this synthesized circuit.
    • Verify the synthesized SystemC model.

  • Use your existing HDL synthesis tool and hardware flow (such as Xilinx XST and Project Navigator) to:

    • Synthesize the generated HDL to working hardware.


Custom FPGA Co-processing and Hardware Acceleration

Using SystemC and SystemCrafter, you can easily develop hardware coprocessing and software acceleration units. Using FPGA hardware, such as the ZestSC1 desktop board, with SystemC flows enables powerful new computing applications.

Using FPGA hardware with SystemCrafter SC allows powerful new computing applications.

You can use your existing C++ compiler to develop a SystemC description of your application, and experiment with implementing parts of the code in different coprocessors and hardware accelerators. You can use your compiler's facilities to profile candidate architectures, and simulate the whole system. Then SystemCrafter will automatically produce RTL VHDL or Verilog descriptions of the hardware, which you can implement in your FPGA.

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